INTRODUCTION:
Metal-oxide semiconductor field-effect transistors (MOSFETs) constitute the basic building block of present-day CMOS technology. The current research in this field is essentially turned toward an increasing of the device density through a destructive scaling of the device-feature sizes. Doping refers to the addition of specific impurities to a semiconductor to modify its electrical properties. The amount of impurities that can be incorporated in Si depends on the solid solubility[1, 2].The gate-tunnelling in the MOSFETs can be reduced with the use of the high-k gate dielectric while in a MOSFET with a channel length of approximately 10 nm, the off-current is a salient value that leads to an increase of the sub-threshold swing (SS) and a lowering of both the drain-induced barrier and the threshold voltage. One of the parameters that improves the short-channel effects and controls the threshold voltage is the channel-doping concentration; for this reason, researchers often apply channel doping of a uniform concentration to control the short-channel effects in MOSFETs ; moreover, it must be noted that the nature of the actual in-practice transistor-channel doping profile becomes closer to that of the Gaussian and Pearson doping profile due to the ion-implantation stages that are required during the fabrication process.
Gaussian Doping Profile
In this scenario, the total amount of dopant atoms at the start of the diffusion process is a constant and the concentration of the atoms at the surface gradually decreases with time. This happens in the case of doping from a solid source that is placed close to the wafer[3, 4]. Let QT be the total amount of dopants on the surface (at start of diffusion) per unit area. Then, the concentration, C(x, t), is given by
This is a Gaussian function, for a constant surface concentration. The change in surface concentration as a function of time can be obtained from equation 6 with x = 0. This gives
Pearson doping Profile
Gaussian distribution is used for symmetric doping. Pearson distribution is used for asymmetrical cases.The Pearson function can be solved by solving the following differential equation:
in which f(x) is the frequency function. The constants a, b0, b1and b2are related to the moments of f(x) by:
, 
, 
, 
where A = 10β −12γ2 −18, with γ and β are the skewness and kurtosis, respectively.
NMOS Device Design Specifications and Virtual Fabrication
For this paper, a 40nm MOSFET was virtually fabricated using SILVACO Athena module and electrical characteristics of the device was simulated using SILVACO Atlas module. The specifications of the device are taken with p-type silicon substrate having doping concentration of 5e15 cm-3and <100> orientation. The substrate is taken with low doping concentration.[5]The p-well implantation was done having Boron with doping concentration of 1e12 cm-3.Then the threshold implant layer was implanted to adjust the threshold voltage of the device. The concentration of threshold implant adjust was considered as 5e12cm-3. The source drain doping concentration was taken as 3.5e15cm-3.After the design and fabrication, the combined structure of fabricated NMOS device with Gaussian and Pearson doping profiles is shown in Figure 1.
Figure 1 Structure of NMOS with Gauss and Pearson doping profile
RESULTS AND DISCUSSIONS:
A 45nm NMOS device with 40nm gate length is designed and fabricated. The comparison of both doping distributions has been done on the basis of ON current, OFF current, on/off current ratio, Substrate current, sub-threshold slope and DIBL [6]. The comparative results have been shown in this section on the basis of simulation results.
A. Absolute Net Doping
The absolute net doping concentration of both profiles is shown in Figure 2.
Figure 2 Absolute net doping of NMOS with Gaussian and Pearson doping profile
The absolute net doping at source and drain ends is shown in Figure 3 below.
Figure 3Absolute net doping of NMOS with Gaussian and Pearson doping profile at Drain/Source
B. Drain current characteristics
The drain current characteristics of 45nm NMOS is simulated in Atlas SILVACO tool and various Drain current versus Gate and Drain Voltage, Gate current versus Drain voltage and Gate voltage, Substrate current versus Gate voltage and Drain voltage. The drain current characteristics are shown in below Figures.
Figure 4 ID versus VDS of NMOS with Gaussian and Pearson doping profile
Figure 5 ID versus VGS of NMOS with Gaussian and Pearson doping profile
Figure 4 and Figure 5 shows the drain current versus drain voltage and gate voltage. It shows the variation of drain current with drain voltage at different gate voltages and drain current with gate voltage with different drain voltages[7,8]. The supply voltage is considered here is 1.2V.The maximum drain current in Gaussian doping profile is estimated 2973μA and for Pearson doping Profile is 2941μA. The variation of gate current with gate and drain voltage is shown in Figure 6 and Figure 7 below.
Figure 6 IG versus VGS of NMOS with Gaussian and Pearson doping profile
Figure 7 IG versus VDS of NMOS with Gaussian and Pearson doping profile
The substrate current characteristics are shown in Figure 8 and Figure 9 below. The estimated substrate current for Gaussian doping profile is 9.46504e-07 and for Pearson doping profile is 1.02065e-06 which is more in this profile.
Figure 8 ISUB versus VGS of NMOS with Gaussian and Pearson doping profile
Figure 9 ISUB versus VDS of NMOS with Gaussian and Pearson doping profile
C. Effect of Gate oxide thickness on Gauss and Pearson doping Profiles of NMOS
The gate oxide thickness plays an important role in scaling of MOSFETs. As the gate oxide thickness is decreased or scaled down, the effect of gate leakage comes into picture. Here, the effect of scaling down of Tox from 2nm to 1nm, with Gaussian and Pearson doping profiles are shown after the simulation of NMOS device [9]. The drain current characteristics are shown in Figure 10, Figure 11 and Figure 12 below.
Figure 10 Gauss and Pearson doping comparison at various tox(Linear mode)
Figure 11 Gauss and Pearson doping comparison at various tox(Log mode)
Figure 12 Gauss and Pearson doping comparison at various tox
The comparative Figures below shows the more precise results after the extraction of parameters after simulation. The Figure 13 shows the two threshold voltages, Vtsat at high drain voltage equals to 1.2V and Vtlin at low drain voltage equals to 0.05V [10]. The Figure 13 shows the both threshold voltages, vtsat and vtlin are more in Pearson doping profile.
Figure 13 Vtsat and Vtlin for Gauss and Pearson doping Profiles
Figure 14 shows that the OFF current is less in NMOS Gaussian doping profile equals to 9.42215nA as compared to Pearson doping profile equals to 6.92924nA.
Figure 14 OFF current for Gauss and Pearson doping Profiles
Figure 15 shows the substrate current in Gaussian doping profiles equals to 9.74e-07 is less as compared to Pearson profile equals to 1.02e-06.
Figure 15 Substrate current for Gauss and Pearson doping Profiles
CONCLUSION:
This paper concludes the design, virtual fabrication, simulation and analysis of a 45nm NMOS device having a gate length of 40nm. The comparison of both Gaussian and Pearson doping profiles is done on the basis of simulation results. It has been observed that Pearson doping profile has less OFF state leakage current equals to 6.92924nA and high threshold voltage and Gaussian doping profile has less substrate current equals to 9.47e-07 and less threshold voltage. The drain current is more in Gaussian doping profile equals to 2973μA. The NMOS device is also simulated with various gate oxide thicknesses.
REFERENCES:
[1] Athena User’s Manual, March 4, 2011.
[2] Mohamed Boubaaya, FayçalHadj Larbi, SlimaneOussalah, "Simulation of Ion Implantation for CMOS 1μm Using SILVACO Tools, Proceedings of The 24th International Conference of Microelectronics, ICM 2012, December 17-20, 2012, Algiers, Algeria
[3] P. Y. Yu and M. Cardona , Fundamentals of Semiconductors (Springer, Berlin, 2010), p. 180.
[4] Neil H. E. Weste and David Money Harris “CMOS VLSI Design A Circuits and Systems Perspective”copyright © 2011, 2005, 1993, 1985 Pearson Education, Inc., publishing as Addison-Wesley
[5] Amar Mukerjee“Introduction to NMOS and CMOS VLSI System Design” copyright © 1986 Prentice Hall Eglewood Cliffs, New Jersey
[6] Ajit Pal “Chap 2 MOS Fabrication Technology” in Low Power VLSI Circuit and System” copyright © 2015 by Springer India
[7] ITRS - International Technology Roadmap for Semiconductor. Austin: Semiconductor Industry Assoc., 2003
[8] Silvaco International, Silvaco: Virtual Wafer Fab,http://www.silvaco.com/products/vwf/vwf.html, Silvaco International, 1995
[9] Sung-Mo Kang, Yusuf Leblebici, (2003)“CMOS digital integrated circuit: analysis and design”, McGarw-Hill Higher Companies, Inc., 3th Edition
[10] Nitin Sachdeva, MunishVashishath, P K Bansal, "Analytical Modelingand Simulation of OFF-state Leakage current for lightly doped MOSFETs" Journal of Nano and Electronic Physics, (2017) Vol. 9, No 6, 06009(4pp)
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Received on 30.01.2018 Accepted on 20.03.2018 © EnggResearch.net All Right Reserved Int. J. Tech. 2018; 8(1): 23-32 DOI:10.5958/2231-3915.2018.00005.6 |
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